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MIPS instruction set
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101	Bluespec Extensible RISC Implementation: BERI Hardware reference Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-07-14 10:37:05 MIPS architecture Instruction set Hardware description language R4000 64-bit Reduced instruction set computing Computer architecture Instruction set architectures Bluespec Inc.
102	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-07-14 10:03:30 MIPS architecture Ring Instruction set 64-bit Hypervisor Reduced instruction set computing Capability-based security Kernel Memory protection Computer architecture Central processing unit Instruction set architectures
103	Microsoft PowerPoint - mescal-chess-kickoff[1].ppt [Read-Only] Add to Reading List Source URL: chess.eecs.berkeley.edu Language: English Instruction set architectures Integrated circuits Field-programmable gate array LEON IXP1200 Embedded system Application-specific integrated circuit MIPS architecture Atmel AVR Computer hardware Electronic engineering Computer architecture
104	MIPS Assembly Language Guide MIPS is an example of a Reduced Instruction Set Computer (RISC) which was designed for easy instruction pipelining. MIPS has a “Load/Store” architecture since all instructions (other than Add to Reading List Source URL: www.cs.uni.edu Language: English - Date: 2008-03-04 08:20:27 Instruction set architectures MIPS architecture Calling convention SPIM Processor register 64-bit Subroutine Computer architecture Computing Computer programming
105	Instruction Sets Should Be Free: The Case For RISC-V Krste Asanović David A. Patterson Electrical Engineering and Computer Sciences Add to Reading List Source URL: www.eecs.berkeley.edu Language: English - Date: 2014-08-06 18:10:49 Instruction set Reduced instruction set computing DEC Alpha IBM POWER ARM architecture OpenRISC VAX 64-bit Computer architecture Instruction set architectures MIPS architecture
106	INTRODUCTION These notes, used in a two-part four-hour short course, introduce the reader (mostly the scientific programmer) to some of the main scalar optimization concepts and techniques associated with modern supersca Add to Reading List Source URL: sc.tamu.edu Language: English - Date: 2006-07-28 17:21:05 Central processing unit R10000 CPU cache Superscalar Software pipelining Instruction set R8000 MIPS architecture Computer hardware Computer architecture Computing
107	1 Three Generations of Asynchronous Microprocessors Alain J. Martin, Mika Nystr¨om, Catherine G. Wong Department of Computer Science Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2003-08-13 19:45:22 Electrical circuits Instruction set architectures MIPS architecture Asynchronous circuit R4000 Quasi Delay Insensitive R4600 Alpha 21064 Central processing unit Computer architecture Electronic engineering Computer hardware
108	Adding custom instructions to the Simplescalar infrastructure Somasundaram Meiyappan HT023601A School of Computing National University of Singapore Add to Reading List Source URL: www.webabode.com Language: English - Date: 2013-12-10 10:54:48 Instruction set architectures Compilers GNU Compiler Collection Programming language implementation Tensilica Instruction set MIPS architecture Retargeting ARM architecture Computer architecture Software Computing
109	Microsoft PowerPoint - Arakawa-Figs-2.ppt [Compatibility Mode] Add to Reading List Source URL: media.wiley.com Language: English - Date: 2013-08-30 13:15:06 Instruction set architectures Microprocessors Parallel computing Classes of computers Multi-core processor MIPS architecture SuperH DEC Alpha Superscalar Computer architecture Computing Computer hardware
110	Microsoft Word - 24KE SPF05 paper current.doc Add to Reading List Source URL: www.imgtec.com Language: English - Date: 2013-10-01 09:04:24 Digital signal processing Instruction set architectures Microprocessors Parallel computing Digital signal processor MIPS architecture Multi-core processor Reduced instruction set computing Delay slot Computer architecture Computer hardware Computing

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